Catapults

HMGCC Co-Creation Challenge: Assurance of printed circuit boards using machine vision

Summary of the challenge

When national security organisations use electronic equipment in sensitive environments, they must be sure every element has been properly assured.

In its latest challenge, HMGCC Co-Creation wants organisations to get involved in a five-month project, developing ways to robustly assure printed circuit boards (PCBs).

The innovative methods used need to image and verify the complete manufactured PCB stack-up, providing assurance they will function where and when they are most needed.

HMGCC Co-Creation will provide funding for time, material, overheads, and other indirect expenses.

A green printed circuit board background with text. The logos for HMGCC Co-Creation and dstl are in the upper left, with the challenge title “Challenge: Printed Circuit Board Assurance” on the right. - CSA Catapult

Key information

  • Budget per single organisation - £80,000
  • Project duration - 5 months
  • Competition opens - Monday 15 July 2024
  • Competition closes - Thursday 29 August at 5pm

 

Context of the challenge

All organisations associated with national security undertake sensitive and classified daily tasks, and there is the invariable need to use electronic equipment. Sensitive equipment may be sourced from a range of suppliers varying from bespoke construction by HMGCC to less well-established third-party routes. With all routes, there is a requirement to conduct due diligence on the constituent parts of an electronic system – ensuring functionality and security.

The focus of this challenge is to non-destructively image and verify printed circuit boards (PCB), specifically focusing on analysing copper traces through both the external and internal stack-up layers of complex multi-layer FR4 PCBs.

Key dates

15 July 2024 - Competition opens

13 August 2024 - Deadline for questions 

20 August 2024 - Clarifying questions answered

29 August 2024 - Competition closes 

9 September 2024 - Applicant notified 

17 September 2024 - Pitch day in Milton Keynes

21 October 2024 - Target project kick off 

 

Who should apply?

This challenge is open to sole innovators, industry, academic and research organisations of all types and sizes. There is no requirement for security clearances.

Solution providers or direct collaboration from countries listed by the UK government under trade sanctions and/or arms embargoes, are not eligible for HMGCC Co-Creation challenges.

 

Evaluation criteria

All proposals, regardless of the application route, will be assessed by the HMGCC Co-Creation team. Proposals will be scored 1–5 on the following criteria:

Scope: Does the proposal fit within the challenge scope, taking into consideration cost and benefit?

Innovation: Is the technical solution credible, will it create new knowledge and IP, or use existing IP?

Deliverables: Will the proposal deliver a full or partial solution, if a partial solution, are there collaborations identified?

Timescale: Will the proposal deliver a minimum viable product within the project duration?

Budget: Are the project finances within the competition scope?

Team: Are the organisation / delivery team credible in this technical area?

Applicants can submit applicants by sending them to collaboration@csa.catapult.org.uk or directly to cocreation@hmgcc.gov.uk.

HMGCC Co-Creation supporting information

HMGCC works with the national security community, UK government, academia, private sector partners and international allies to bring engineering ingenuity to the
national security mission, creating tools and technologies that drive us ahead and help to protect the nation.

HMGCC Co-Creation is a partnership between HMGCC and Dstl (Defence Science and Technology Laboratory), created to deliver a new, bold and innovative way of
working with the wider UK science and technology community. We bring together the best in class across industry, academia, and government, to work collaboratively on national security engineering challenges and accelerate innovation.

HMGCC Co-Creation is part of the NSTIx Co-Creation network, which enables the UK government national security community to collaborate on science, technology
and innovation activities and to deliver these in partnership with a more diverse set of contributors for greater shared impact and pace.

HMGCC Co-Creation aims to work collaboratively with the successful solution providers by utilising in-house delivery managers working Agile by default. This
process will involve access to HMGCC Co-Creation’s technical expertise and facilities to bring a product to market more effectively than traditional customer/supplier relationships.

Full challenge information 

Terms and conditions 

FAQ

 

The competition talks about imaging PCBs in the range of visible and x-ray light. Would the Authority consider approaches that use longer wavelengths of electromagnetic energy under this challenge?

There is no restriction on the wavelengths to use to image PCBs and the solution can include
multispectral imaging, provided it can be done safely. The solution to imaging should include a
method to image the internal copper traces of the PCB.

Is the use of ML vision processing in solutions considered mandatory?

The use of ML is not mandatory, all valid approaches to interpreting the images are encouraged
and assessed equally.

Do we have access to any data / circuit boards / CT scanners / X ray machines, or do we have to source everything ourselves?

CT radiograph and reconstruction volume data of a small number of PCBs can be provided.
Commercial PCBs with open source design data are also available.

Can we build a computer model in unity to show how this would work in practice or do you need a physical PoC?

Could you explain more about what you are thinking with building a computer model in unity?
Ideally would like a PoC, though we don’t understand enough about the unity approach to give a definitive answer.

Is 80k the limit for this work?

For this phase yes. At the end of the phase the work completed will be reviewed against existing
budget allocations. So there is potential for further funding at a later date.

Can we use off the shelf data processing programs like FME, Hadoop, MATLAB or do we have to build it all from scratch?

In the final application, data processing will preferably be done off-line. While there are no
limitations to which data processing approach to use, being able to run it off-line will be of
benefit.

Is there anything we’re not allowed to use?

I would like to leave the solution open to not constrain creative ideas. Please feel free to ask
about anything you think might fall into this category of not allowed.

Do we have test data or test items we know are tempered or are not tampered to use as QA for the design process.

A small set of CT data and gerber manufacturing data for tampered/not tampered PCBs can be
provided, though other options should be explored first.

What datasets are available for AI modelling? As this is a key limiting factor within the tight delivery timeframes to developing a sophisticated AI. EG, are there datasets of PCB Xray/CT images linked to CAD files? And if so, what's the rough size of the available data (in terms of number of samples)?

We will not be providing large datasets for AI training purposes, however a small set of CT data
and gerber manufacturing data for tampered/not tampered PCBs can be provided.

If no datasets are available, this presents an opportunity to deploy a novel imaging
technology that we've been developing (redacted). We believe this technology (redacted) has particular relevance for establishing the integrity of copper tracks on a pcb, but the lack of existing datasets poses a concern for success AI development. Nonetheless, we believe we could develop a demonstrator in the timeframes, but this would be on non-populated PCBs (with further work then required to upgrade the solution to work on populated PCBs). Would this be an acceptable end point for the project?

Tracing of copper tracks and their attribution across multi-layered PCBs with a development
pathway of how this can be applied to populated PCBs to overcome problems should as
‘shadowing’ is of interest.

What are the dimensions and thickness of the PCB board?

PCB dimensions could be up to 30cm by 20 cm, more likely smaller 15cm x 10 cm. Thickness up to 2mm but more likely 1mm to 1.5mm.

Which types of X-Ray technology or machines have been attempted?

Micro-focus CT scanning up to 200KeV.

What were the limitations of the existing X-ray technology that was used?

Component’s metal artefacts “shadow” images, high barrier to entry on machine cost and user
training. Can be difficult to manually interpret volume.

What is the minimum size of the copper traces that can be analysed?

Each copper trace could be less than 35um in height, less than 100um in width and a copper clad layer less than 150um thick.

How many copper layers are typically found in an assembly, and what is the maximum number observed?

A PCB for verification could consist of multiple (potentially 10 or more) layers of copper traces,
bonded on to FR4 glass epoxy substrates and laminated together.

What is the closest dielectric separation between copper layers?

Pre-preg thickness between layers minimum would be 50um though likely to be 100um.

Where are the copper traces located within the PCB board?

Traces would be on layers spread through out the PCB stack up. Some layers will be planes of
copper for power and ground low impedance distribution, while other layers will be signal layers with mostly copper traces surrounded copper planes of power and ground for signal and power integrity.

While the goal is to focus on an image-based solution can some limited probing take place?

Absolutely, the goal is to determine the tracking layout and if probing benefits the solution
understanding then yes.

Would we be able to power the PCB board under test?

Yes

Is there an expected limit to the cost of the final system once production ready?

No cost is currently defined to not constrain potential solutions. It is envisaged the system would be R&D lab equipment scale.